Staggering of openings in electrodes for crack mitigation

ABSTRACT

A transducer comprising: at least one piezoelectric layer; a first patterned conductive layer that is patterned with a first opening; a second patterned conductive layer that is patterned with a second opening; wherein at least one piezoelectric layer is between the first and the second patterned conductive layers in a stack; and wherein a position of the first opening is staggered relative to a position of the second opening in the stack to mitigate an occurrence of crack propagation through the layers.

CLAIM OF PRIORITY

This application claims the benefit of priority under 35 U.S.C. § 119(e) to provisional U.S. Patent Application No. 62/049,091, filed on Sep. 11, 2014, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Micro-electro-mechanical systems (MEMS) technology has enabled the development of acoustic transducers (as described in U.S. Pat. Nos. 8,531,088 and 9,055,372, the entire contents of each of which are incorporated herein by reference), such as microphones using silicon-wafer deposition techniques. Microphones fabricated this way are commonly referred to as MEMS microphones and can be made in various forms such as capacitive microphones or piezoelectric microphones. MEMS capacitive microphones and electret condenser microphones (ECMs) are used in consumer electronics and have an advantage over typical piezoelectric MEMS microphones in that they have historically had greater sensitivity and lower noise floors. However, each of these more ubiquitous technologies has its own disadvantages. For standard ECMs, they cannot be mounted to a printed circuit board using the typical lead-free solder processing commonly used to attach microchips to the board. MEMS capacitive microphones, which are often used in cell phones, have a backplate that is a source of noise in the microphones. MEMS capacitive microphones also have a smaller dynamic range than typical piezoelectric MEMS microphones.

SUMMARY

In some examples, a transducer comprises at least one piezoelectric layer; a first patterned conductive layer that is patterned with a first opening; a second patterned conductive layer that is patterned with a second opening; wherein at least one piezoelectric layer is between the first and the second patterned conductive layers in a stack; and wherein a position of the first opening is staggered relative to a position of the second opening in the stack to mitigate an occurrence of crack propagation through the layers.

In this example, the first and second patterned conductive layers are patterned on a moving portion of the transducer to generate more than four sensor elements on the transducer. A sensor element comprises more than sixty-percent piezoelectric material. Each of the first and second conductive layers are electrodes, wherein the first and second openings are staggered about an axis that represents a substantially optimal point for breaking the electrodes to increase an amount of output energy of the transducer. The first and second openings are staggered such that a vertical traversal between the openings is against a grain of piezoelectric material in the at least one piezoelectric layers. An angle formed by a line representing the vertical traversal and a base of a conductive layer is less than or greater than an angle at which a crack propagates through the at least one piezoelectric layer. The transducer is an acoustic transducer, a microphone or a piezoelectric MEMS transducer. Each of the first and second openings have a width of substantially six microns.

In another example, a method includes patterning a first electrode layer deposited on a substrate with a first opening in the first electrode layer; depositing a piezoelectric layer on the patterned first electrode layer; depositing a second electrode layer on the piezoelectric layer; and patterning the deposited second electrode layer with a second opening, with a placement of second opening in the second electrode layer being staggered relative to a placement of the first opening in the first electrode layer to mitigate a probability of a crack traversing from the first electrode layer, through the piezoelectric layer and to the second electrode layer. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

In this example, the first electrode layer, the piezoelectric layer and the second electrode layer comprise a stack, and wherein the method further comprises: determining a location of an axis through the stack that represents a substantially optimal point for breaking the first and second electrode layers to increase an amount of output energy of a device comprising the stack, relative to another amount of output energy when the axis is at another location. The actions include based on a grain of piezoelectric material in the at least on piezoelectric layer, determining a linear traversal route of a crack through the piezoelectric material that occurs with a decreased amount of frequency, relative an amount of frequency of other linear traversal routes through the piezoelectric material. The actions include determining a location of the first opening relative to the axis by determining a location in the first electrode layer that intersects the linear traversal route, when the linear traversal route intersects the axis substantially in a middle of the axis. The actions include determining a location of the second opening relative to the axis by determining a location in the second electrode layer that intersects the linear traversal route, when the linear traversal route intersects the axis substantially in the middle of the axis. An angle formed by the linear traversal route intersecting the first electrode layer at a base of the first electrode layer is less than or greater than an angle at which a crack propagates through the piezoelectric layers. The actions include fabricating a piezoelectric device by the patterning and depositing actions. The piezoelectric device comprises a piezoelectric transducer, a piezoelectric acoustic transducer, or a piezoelectric microphone.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE FIGURES

FIGS. 1-2 are each diagrams of plates.

FIGS. 3A-3E are each diagrams of a piezoelectric MEMS device.

FIGS. 4 and 5 are flowcharts of processes for fabricating transducers with staggered openings in electrode layers.

DETAILED DESCRIPTION

Referring to FIG. 1, diagram 10 is a bird's eye view of beam 11 that includes a piezoelectric layer sandwiched between two electrode layers. In this example, beam 11 is included in an acoustic transducer. The top of beam 11 is an electrode layer with break or opening 12 in the electrode layer. Break 12 promotes optimal performance of beam 11, by preventing all the capacitance from being at the end of beam 11, where there is no sensitivity. If all the capacitance was at the end of beam 11, beam 11 would provide minimal energy. Therefore, the electrode layer is broken to have optimal performance of beam 11 and a sensor that includes beam 11. If all the breaks in the layers in beam 11 were aligned, beam 11 would be very fragile and prone to breaking. Accordingly, the breaks (or openings) are staggered to preserve the structural integrity of beam 11 and reduce breakage.

Referring to FIG. 2, an arrangement of metal patterning for crack mitigation in piezoelectric Microelectromechanical systems (MEMS) devices is shown. In this example, plate 20 (or a beam) includes electrode layers 21, 23, 25 and piezoelectric layers 22, 24. When building piezoelectric MEMS devices, the piezoelectric material is often relatively brittle and is susceptible to cracking. It is especially susceptible to cracking when a large portion of the sensor film stack (e.g., layers 21-25) includes a piezoelectric material. For example, when a sensor is built with a thin piezoelectric layer on a much thicker silicon (Si) plate, the durability of the sensor is largely determined by the durability of the thicker Si. When the sensor includes more than a predefined amount of piezoelectric material (e.g., more than 60% piezoelectric material, more than 40-70% piezoelectric material and so forth), the sensor durability is largely determined by the durability of the piezoelectric material. In the example of FIG. 2, the durability of plate 20 is substantially determined by the durability of the piezoelectric material.

When a metal layer (e.g., layer 21) covering the piezoelectric material is patterned as shown, crack initiation is reduced and likelihood of crack propagation is reduced, relative to cracking and propagation when piezoelectric material is not covered in metal. When stacking layers of patterned electrodes 21, 23, 25 and piezoelectric layers 22, 24, openings 26, 27, 28 in metal layers 21, 23, 25, respectively, are staggered so that openings are not in any vertical alignment when viewed from the upper surface of the patterned electrode. This staggering of openings 26, 27, 28 in stacks of patterned electrodes 21, 23, 25 on piezoelectric layers 22, 24 for a MEMS device greatly reduces crack propagation as a failure mechanism in such piezoelectric MEMS devices.

In this example, the metal (e.g., electrode layers 21, 23, 25) is patterned such that openings 26, 27, 28 in the metal pattern are staggered, rather than being aligned along a normal axis in the MEMS device. The metal is patterned by masking a portion of the piezoelectric material and then applying an electrode material (i.e., the metal). The mask is removed, revealing an opening (e.g., one of openings 26, 27, 28). In another example, the metal (e.g., one of electrode layers 21, 23, 25) is patterned by depositing the electrode material, masking a portion of the layer, and then removing the metal in unmasked areas, e.g., by etching away the metal in the unmasked areas.

In this example, axis 30 illustrates an optimal placement of openings in layers 21, 23, 25, e.g., to ensure optimal performance of plate 20. The location 30 a of axis 30 (in the stack of layers 21-25) is determined in accordance with the optimization parameter, which is:

${{Optimization}\mspace{14mu}{Parameter}} = {\frac{V_{out}^{2}C}{P^{2}{{Atan}(\delta)}} \cdot f_{res}^{2}}$

In this example, A is the sensor area (e.g., the area of plate 20 that is electrically connected to the rest of the transducer or base). In this example, the sensor area A, resonance frequency f_(res), dissipation factor tan(d), and input pressure P are constant. The capacitance C and output voltage V_(out) are determined by the locations of electrode breaks (i.e., openings) 27 and 28. As the length from the base of the plate to the electrode breaks 27 and 28 is increased, the capacitance will increase and the output voltage will decrease. As the length from the base of the plate to the electrode breaks 27 and 28 is decreased, the capacitance will decrease and the output voltage will increase. Based on this, the product of capacitance and the squared output voltage is maximized, at optimal locations of breaks 27, 28. In this example, all variables are constant except for Gut and C. A value of the optimization parameter is determined by determining values of Gut and C that result in an increased value for the optimization parameter, relative to other values of the optimization parameter at other values of V_(out) and C. In this example, axis 30 is located at location 30 a, which is a location in the stack at which a length of the sensor area A is length 33. In this example, if all the breaks are aligned with axis 30, plate 20 would be very fragile. In this example, axis 30 could be located in various portions of the stack. The particular location 30 a is determined in accordance with the foregoing optimization equation, e.g., by determining an optimal location for the electrode breaks.

To promote durability of plate 20, openings 26, 27, 28 are staggered about axis 30. In this example, openings 26, 27, 28 are spread out enough to provide crack mitigation, but not spread out too far away from axis 30 that performance substantially declines. In particular, openings 26, 27, 28 are staggered in accordance with a slope of line 31 (e.g., a slope of 0.1). In this example, the slope of line 31 is predetermined in accordance with a grain of materials used in plate 20, e.g., a grain of piezoelectric material in layers 22, 24. In this example, line 31 represents a linear traversal route of a crack that is unlikely to occur, given the grain pattern of the piezoelectic material. Based on the grain, a slope (e.g., of a linear traversal route) is selected that is sufficiently against the grain that breakage is prevented. In this example, a ninety degree angle (θ) is less than ideal, because at this angle the piezoelectric material is very prone to breakage. However, if the angle is very small, the locations of the staggered breaks are less than ideal (even though breakage is very unlikely at a small angle), because this results in breaks in the electrodes that are further away from axis 30 and thus a decreased value for the optimization parameter. Accordingly, an angle is selected that is less than ninety degrees but still large enough to provide an acceptable optimization parameter (i.e., the selected value for the angle results in at least a threshold optimization parameter), e.g., based on values of Gut and C that result from breaks with locations that are determined from the selected angle.

As shown in FIG. 2, an angle (θ) formed by the linear traversal route (e.g., line 31) intersecting a first electrode layer 25 at a base of first electrode layer 25 is less than or greater than an angle at which a crack propagates through the piezoelectric layer 24. In this example, the angle is 5.7 degrees. Because AIN has primarily 0002 orientation, the grain boundaries are primarily at 90 degrees to the substrate surface. An alignment of openings in the vertical direction, therefore, is the worst case for vertical crack propagation and smaller angles will do more to inhibit crack propagation. The best optimization parameter is achieved when openings 27 and 28 are aligned because the optimal location for an electrode break is the same for all layers. Therefore, it is desireable to find some angle at which the crack propagation is significantly inhibited but the optimization parameter is not significantly reduced. Because the optimization parameter does not vary sharply about its maximum, this allows for a relatively large design space. Therefore, we have selected a 10:1 ratio of break separation to film thickness resulting in an angle of 5.7 degrees. In this example, a piezoelectric layer has a thickness of 500 nanometers. In this example, the breaks are separated from each other by Sum, in accordance with the 10:1 ratio. The placement of openings 26, 27, 28 is determined by intersecting line 31 with axis 30, e.g., in a center of axis 30. In this example, a vertical traversal of a break (e.g., in accordance with line 31) is less likely than a vertical traversal of a break along axis 30. In this example, the width of a break (e.g., break 26) is of various lengths, including, e.g., six microns. The length of the break is determined by studying the trade-off between crack mitigation and stray capacitance. If the break is too wide, although the breaks are off-set, a vertical opening in the electrode material through the entire film stack will still result. If the break is too narrow, the plates will be coupled through fringing fields, leading to unwanted stray capacitance. Again, the design space is somewhat large and we have selected 6 um as a safe spacing to avoid significant stray capacitance. In this example, the performance of plate 20 is based on individual performance of layers 21, 22, 23, with electrode openings 26, 27, and individual performance of layers 23, 24, 25, with electrode openings 27, 28. The combination (e.g., average) of these individual performances provides a performance that is substantially the same as a performance that would be obtained by breaks or openings aligned along axis 30.

Referring to FIGS. 3A-3C, first and second patterned conductive layers are patterned on a moving portion of a piezoelectric MEMS device to generate more than four sensor elements on the piezoelectric MEMS device. These four sensor elements are included in an acoustic transducer or microphone.

Referring now to FIG. 3A, beam 40 is fabricated on substrate 42. FIG. 3A provides a top or bird's eye view of the beam. Beam 40 includes layer 44, which is a first patterned conductive or electrode layer. The pattern of layer 44 includes break 46 for crack mitigation and break 48 to segment an active area of the electrode layers. The active area of the electrode layers is segmented because these various active areas will later be wired in series to trade-off sensor output voltage with sensor capacitance. Layer 44 also includes breaks 47, 49, which are ending points for layer 44 and are for crack mitigation, leaving portions 41, 43 of a piezoelectric material that is sandwiched between layers 44, 50 (FIG. 3B). In this example, the middle electrode is broken over portions 41, 43, with the top and bottom electrodes being unbroken over portions 41, 43. Referring to FIG. 3B, beam 40 is built up with second layer 50, which is a second patterned conductive (or electrode) layer. Layer 50 includes breaks 51, 52, 53 for crack mitigation and break 54 to segment the active areas of the electrode. FIG. 3C illustrates the portions of the first and second patterned conductive layers 44, 50 that overlap and moving portion 60 of beam 40. Generally, a moving portion is one or more mechanical moving elements on a MEMS device. FIG. 3C provides a transparent view of the top of beam 40 to enable visualization of the various layers and breaks in beam 40. In this example, layer 44 is visually shown through break 52 in layer 50, as is shown by the thatching in FIG. 3C. Layer 50 is visually shown relative to break 46 in layer 44. In this example, breaks 46, 52 are staggered relative to each other for crack mitigation.

Based on the crack mitigation that results from staggering the breaks, a sensor has a decreased amount of fragile areas, e.g., relative to an amount of fragile area of a sensor that is produced with the breaks aligned together. Using the techniques described herein, a fragile area is less than 50% of the sensor area. In particular, all of the plate is either Area X or Area Y so it adds up to 100%. The “fragile area” is either area X or islands of Area Y that do not extend to the substrate. There are no islands of Area Y in this example. An island of Area Y would be an Area Y that is completely surrounded by Area X and does not overlap with the substrate.

Referring to FIG. 3D, beam 40 includes areas 70, 72 (i.e., areas X), which are fragile areas. An Area X is an area on the moving portion of a piezoelectric device that includes only piezoelectric material when looking from the top-down. Referring to FIG. 3E, beam 40 includes non-fragile area 76, e.g., area Y that does extend to a substrate on which the piezoelectric MEMS device is built. An area Y is all of the areas on the moving portion of a piezoelectric device that is not Area X.

Referring to FIG. 4, process 80 is implemented (e.g., by one or more processing devices, fabrication devices, or other electronic systems) in fabricating a transducer. In operation, the device patterns (82) a first electrode layer deposited on a substrate with a first opening (e.g., opening 28) in the first electrode layer. The device deposits (84) a piezoelectric layer on the patterned first electrode layer and deposits (86) a second electrode layer on the piezoelectric layer. The device also patterns (88) the deposited second electrode layer with a second opening (e.g., opening 27), with a placement of the second opening in the second electrode layer being staggered relative to a placement of the first opening in the first electrode layer to mitigate a probability of a crack traversing from the first electrode layer, through the piezoelectric layer and to the second electrode layer.

Referring to FIG. 5, process 90 is implemented (e.g., by an electronic system or another entity) in identifying a placement of the openings in the electrode layers. In operation, the first electrode layer, the piezoelectric layer and the second electrode layer is a stack. In this example, the system or entity determines (92) a location of an axis (e.g., axis 30) through the stack that represents a substantially optimal point for breaking the first and second electrode layers to increase an amount of output energy of a device comprising the stack, relative to another amount of output energy when the axis is at another location. Based on a grain of piezoelectric material in the at least one piezoelectric layer, the system or entity determines (94) a linear traversal route (e.g., route 31) of a crack through the piezoelectric material that occurs with a decreased amount of frequency, relative an amount of frequency of other linear traversal routes through the piezoelectric material. The system or entity determines (96) a location of the first opening (e.g., opening 28) relative to the axis by determining a location in the first electrode layer that intersects the linear traversal route, when the linear traversal route intersects the axis substantially in a middle of the axis. The system or entity also determines (98) a location of the second opening (e.g., opening 27) relative to the axis by determining a location in the second electrode layer that intersects the linear traversal route, when the linear traversal route intersects the axis substantially in the middle of the axis.

Embodiments can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations thereof. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits).

Other embodiments are within the scope and spirit of the description and the claims. For example, the techniques described herein can be applied to various types of devices, including, e.g., a (MEMS) device, an accelerometer, a transducer, an acoustic sensor, a sensor, a microphone or a gyroscope. Additionally, the techniques described herein for damping a resonance frequency may also be used to adjust a resonance frequency and to increase a resonance frequency.

Additionally, due to the nature of software, functions described above can be implemented using software, hardware, firmware, hardwiring, or combinations of any of these. The use of the term “a” herein and throughout the application is not used in a limiting manner and therefore is not meant to exclude a multiple meaning or a “one or more” meaning for the term “a.” Additionally, to the extent priority is claimed to a provisional patent application, it should be understood that the provisional patent application is not limiting but includes examples of how the techniques described herein may be implemented.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the claims and the examples of the techniques described herein. 

What is claimed is:
 1. A transducer comprising: at least one piezoelectric layer; a first patterned conductive layer that is patterned with a first opening; a second patterned conductive layer that is patterned with a second opening; wherein at least one piezoelectric layer is between the first and the second patterned conductive layers in a stack; and wherein a position of the first opening is staggered relative to a position of the second opening in the stack such that a vertical traversal between the first and second openings is against a grain of piezoelectric material in the at least one piezoelectric layer to mitigate an occurrence of crack propagation through the layers.
 2. The transducer of claim 1, wherein the first and second patterned conductive layers are patterned on a moving portion of a transducer to generate more than four sensor elements on the transducer.
 3. The transducer of claim 2, wherein a transducer includes a sensor element that comprises more than sixty-percent piezoelectric material.
 4. The transducer of claim 1, wherein each of the first and second conductive layers are electrodes, wherein the first and second openings are staggered about an axis that represents a substantially optimal point for breaking the electrodes to increase an amount of output energy of a transducer.
 5. The transducer of claim 1, wherein an angle formed by a line representing the vertical traversal and a base of a conductive layer is less than or greater than an angle at which a crack propagates through the at least one piezoelectric layer.
 6. The transducer of claim 1, wherein a transducer is an acoustic transducer, a microphone or a piezoelectric MEMS transducer.
 7. The transducer of claim 1, wherein each of the first and second openings have a width of substantially six microns.
 8. A transducer comprising: at least one piezoelectric layer; a first conductive layer with a first opening; and a second conductive layer with a second opening; wherein the at least one piezoelectric layer is between the first and the second conductive layers; and wherein a vertical traversal between the first and second openings is against a grain of piezoelectric material in the at least one piezoelectric layer.
 9. The transducer of claim 8, wherein the first and second conductive layers are patterned on a moving portion of a transducer to generate more than four sensor elements on the transducer.
 10. The transducer of claim 8, wherein a transducer includes a sensor element that comprises more than sixty-percent piezoelectric material.
 11. The transducer of claim 8, wherein each of the first and second layers are electrodes, wherein the first and second openings are staggered about an axis that represents a substantially optimal point for breaking the electrodes to increase an amount of output energy of a transducer.
 12. The transducer of claim 8, wherein an angle formed by a line representing the vertical traversal and a base of a conductive layer is less than or greater than an angle at which a crack propagates through the at least one piezoelectric layer.
 13. The transducer of claim 8, wherein a transducer is an acoustic transducer, a microphone or a piezoelectric MEMS transducer.
 14. The transducer of claim 8, wherein each of the first and second openings have a width of substantially six microns. 